Adding Intelligence to Internet

            Satellites have been used for years to provide communication network links.  Historically, the use of satellites in the Internet can be divided into two generations. In the first generation, satellites were simply used to provide commodity links (e.g., T1) between countries. Internet Protocol (IP) routers were attached to the link endpoints to use the links as single-hop alternatives to multiple terrestrial hops. Two characteristics marked these first-generation systems: they had limited bandwidth, and they had large latencies that were due to the propagation delay to the high orbit position of a geosynchronous satellite.

            In the second generation of systems now appearing, intelligence is added at the satellite link endpoints to overcome these characteristics.  This intelligence is used as the basis for a system for providing Internet access engineered using a collection or fleet of satellites, rather than operating single satellite channels in isolation. Examples of intelligent control of a fleet include monitoring which documents are delivered over the system to make decisions adaptively on how to schedule satellite time; dynamically creating multicast groups based on monitored data to conserve satellite bandwidth; caching documents at all satellite channel endpoints; and anticipating user demands to hide latency.

            This paper examines several key questions arising in the design of a satellite-based system:

Ø  Can international Internet access using a geosynchronous satellite be competitive with today's terrestrial networks?

Ø  What elements constitute an "intelligent control" for a satellite-based Internet link?

Ø  What are the design issues that are critical to the efficient use of satellite channels?

            The paper is organized as follows. The next section, Section 2, examines the above questions in enumerating principles for second-generation satellite delivery systems. Section 3 presents a case study of the Internet Delivery System (IDS), which is currently undergoing worldwide field trials. 

Adaptive Piezoelectric energy harvesting circuit

                   The need for a wireless electrical power supply has spurred an interest in piezoelectric energy harvesting, or the extraction of electrical energy using a vibrating piezoelectric device. Examples of applications that would benefit from such a supply are a capacitively tuned vibration absorber ,a foot-powered radio” tag and a Pico Radio .A vibrating piezoelectric device differs from a typical electrical power source in that its internal impedance is capacitive rather than inductive in nature, and that it may be driven by mechanical vibrating amplitude and frequency. While there have been previous approaches to harvesting energy generated by a piezoelectric device there has not been an attempt to develop an adaptive circuit that maximizes power transfer from the piezoelectric device. The objective of the research described herein was to develop an approach that maximizes the power transferred from a vibrating piezoelectric transducer to an electromechanical battery. The paper initially presents a simple model of piezoelectric transducer. An ac-dc rectifier is added and the model is used to determine the point of optimal power flow for the piezoelectric element. The paper then introduces an adaptive approach to achieving the optimal power flow through the use of a switch-mode dc-dc converter. This approach is similar to the so-called maximum power point trackers used to maximize power from solar cells. Finally, the paper presents experimental results that validate the technique. 

Bi CMOS Technology

            The history of semiconductor devices starts in 1930’s when Lienfed and Heil first proposed the mosfet. However it took 30 years before this idea was applied to functioning devices to be used in practical applications, and up to the late 1980 this trend took a turn when MOS technology caught up and there was a cross over between bipolar and MOS share.CMOS was finding more wide spread use due to its low power dissipation, high packing density and simple design, such that by 1990 CMOS covered more than 90% of total MOS scale.

              In 1983 bipolar compatible process based on CMOS technology was developed and BiCMOS technology with both the MOS and bipolar device fabricated on the same chip was developed and studied. The objective of the BiCMOS is to combine bipolar and CMOS so as to exploit the advantages of both at the circuit and system levels. Since 1985, the state-of-the-art bipolar CMOS structures have been converging. Today BiCMOS has become one of the dominant technologies used for high speed, low power and highly functional VLSI circuits especially when the BiCMOS process has been enhanced and integrated in to the CMOS process without any additional steps. Because the    process step required for both CMOS and bipolar are similar, these steps cane be shared for both of them.

3- D ICs

          There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips.

           

            Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies on one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.

           

            The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC) design.  By simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved.

            In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.

wireless ad hoc sensor networks

       A wireless ad hoc sensor network consists of a number of sensors spread across a geographical area.  Each sensor has wireless communication capability and some level of intelligence for signal processing and networking of the data.

        A wireless ad hoc network is a decentralized wireless network. The network is ad hoc because each node is willing to forward data for other nodes, and so the determination of which nodes forward data is made dynamically based on the network connectivity. This is in contrast to wired networks in which routers perform the task of routing. It is also in contrast to managed (infrastructure) wireless networks, in which a special node known as an access point manages communication among other nodes

        The decentralized nature of wireless ad hoc networks makes them suitable for a variety of applications where central nodes can't be relied on, and may improve the scalability of wireless ad hoc networks compared to wireless managed networks, though theoretical and practical limits to the overall capacity of such networks have been identified.

        Minimal configuration and quick deployment make ad hoc networks suitable for emergency situations like natural disasters or military conflicts. The presence of a dynamic and adaptive routing protocol will enable ad hoc networks to be formed quickly.